AD9995KCPRL datasheet(12/60 Pages) AD

No. de pieza	AD9995KCPRL

Descripción Electrónicos	12-Bit CCD Signal Processor with Precision Timing ??Generator

PDF	60 Pages

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Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

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AD9995

–12–

P[0]

PIXEL

PERIOD

H1/H3

RGf[12]

P[48] = P[0]

Hf[24]

CCD

SIGNAL

P[24]

P[12]

P[36]

Hr[0]

RGr[0]

SHD[0]

NOTES

ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

POSITION

tS1

H2/H4

SHP[24]

Figure 7. High SpeedTiming Default Locations

NOTES

DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

OUTPUT DELAY (

tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

P[0]

P[48] = P[0]

PIXEL

PERIOD

P[12]

P[24]

P[36]

DOUT

DCLK

tOD

Figure 8a. Digital Output Phase Adjustment

NOTES

DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0.

HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

DCLK

DOUT

CCDIN

CLI

SHD

(INTERNAL)

N+1

N+2

N+12

N+11

N+10

N+9

N+8

N+7

N+6

N+5

N+4

N+3

N+13

N–13

N–3

N–4

N–5

N–6

N–7

N–8

N–9

N–10

N–11

N–12

N–2

N–1

N+1

SAMPLE PIXEL N

PIPELINE LATENCY=11 CYCLES

tCLIDLY

N–1

N+2

Figure 8b. Pipeline Delay

REV. 0

AD9995KCPRL Datasheet(PDF) 12 Page - Analog Devices

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