AD9516-3SLASHPCBZ datasheet(49/84 Pages) AD

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AD9516-3

Rev. 0 | Page 49 of 84

INPUT TO CLK

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

910

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 56. SYNC Timing when VCO Divider Is Not Used—CLK Input Only

A SYNC operation brings all outputs that have not been

excluded (by the nosync bit) to a preset condition before

allowing the outputs to begin clocking in synchronicity. The

preset condition takes into account the settings in each of the

channel’s start high bit and its phase offset. These settings

govern both the static state of each output when the SYNC

operation is happening and the state and relative phase of the

outputs when they begin clocking again upon completion of the

SYNC operation. Between outputs and after synchronization,

this allows for the setting of phase offsets.

The AD9516 outputs are in pairs, sharing a channel divider per

pair (two pairs of pairs, four outputs, in the case of CMOS). The

synchronization conditions apply to both outputs of a pair.

Each channel (a divider and its outputs) can be excluded from

any SYNC operation by setting the nosync bit of the channel.

Channels that are set to ignore SYNC (excluded channels) do

not set their outputs static during a SYNC operation, and their

outputs are not synchronized with those of the nonexcluded

channels.

Clock Outputs

The AD9516 offers three output level choices: LVPECL, LVDS,

and CMOS. OUT0 to OUT5 are LVPECL differential outputs;

and OUT6 to OUT9 are LVDS/CMOS outputs. These outputs

can be configured as either LVDS differential or as pairs of

single-ended CMOS outputs.

LVPECL Outputs: OUT0 to OUT5

The LVPECL differential voltage (VOD) is selectable (from

~400 mV to 960 mV, see 0xF0:5<3:2>. The LVPECL outputs

have dedicated pins for power supply (VS_LVPECL), allowing

a separate power supply to be used. VS_LVPECL can be from

2.5 V to 3.3 V.

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVPECL output can be powered

down or powered up as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have several power-down

modes. This includes a safe power-down mode that continues

to protect the output devices while powered down, although it

consumes somewhat more power than a total power-down. If

the LVPECL output pins are terminated, it is best to select the

safe power-down mode. If the pins are not connected (unused),

it is acceptable to use the total power-down mode.

GND

3.3V

OUT

Figure 57. LVPECL Output Simplified Equivalent Circuit

AD9516-3/PCBZ Datasheet(PDF) 49 Page - Analog Devices

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