TSL27721 datasheet(12/58 Pages) OSRAM

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Datasheet, Public

Page 11

[v2-00] 2023-Mar-30

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TSL2772 − Absolute Maximum Ratings

Figure 11:

Wait Characteristics, VDD = 3V, TA = 25°C, WEN = 1 (unless otherwise noted)

Note(s):

1. Parameter ensured by design and is not tested.

Figure 12:

AC Electrical Characteristics, VDD = 3 V, TA = 25°C, (unless otherwise noted)

Note(s):

1. Specified by design and characterization; not production tested.

Parameter

Test

Conditions

Channel

Min

Typ

Max

Unit

Wait step size

WTIME = 0xFF

2.58

2.73

2.9

Wait number of integration steps (1)

1256

steps

Symbol

Parameter (1)

Test

Conditions

Min

Typ

Max

Unit

f(SCL)

Clock frequency (I²C only)

400

kHz

t(BUF)

Bus free time between start and stop

condition

1.3

μs

t(HDSTA)

Hold time after (repeated) start

condition. After this period, the first

clock is generated.

0.6

μs

t(SUSTA)

Repeated start condition setup time

0.6

μs

t(SUSTO)

Stop condition setup time

0.6

μs

t(HDDAT)

Data hold time

μs

t(SUDAT)

Data setup time

100

t(LOW)

SCL clock low period

1.3

μs

t(HIGH)

SCL clock high period

0.6

μs

Clock/data fall time

300

Clock/data rise time

300

Input pin capacitance

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