PCF85103C-2 datasheet(8/20 Pages) PHILIPS

8 / 20 page

2000 Feb 15

Philips Semiconductors

Product speciﬁcation

256

× 8-bit CMOS EEPROMs with

I2C-bus interface

PCF85102C-2; PCF85103C-2

8.3

Device addressing

Following a START condition, the bus master must output

the address of the slave it is accessing. The four MSBs of

the slave address are the device type identifier (see Fig.4

and Fig.5). For the PCF85102C-2, this is fixed to ‘1010’,

for the PCF85103C-2 to ‘0010’.

The next three significant bits address a particular device

or memory page (page = 256 bytes of memory). A system

could have up to sixteen PCF8510xC-2 devices on the

bus. This can be achieved with eight PCF85102C devices

and eight PCF85103C devices, combined on one I2C-bus.

The eight addresses are defined by the state of the A0, A1

and A2 inputs per type.

The last bit of the slave address defines the operation to

be performed. When set to logic 1, a read operation is

selected.

Address bits must be connected to either VDD or VSS.

8.3.1

REMARK

The I2C-bus device select address ‘0010’ is not exclusively

reserved for device PCF85103C-2. Therefore, multiple

use has to be checked in advance.

8.4

Write operations

8.4.1

BYTE/WORD WRITE

For a write operation, the PCF8510xC-2 requires a second

address field. This address field is a word address

providing access to the 256 words of memory. On receipt

of the word address, the PCF8510xC-2 responds with an

acknowledge and awaits the next eight bits of data, again

responding with an acknowledge. The word address is

automatically incremented. The master can now terminate

the transfer by generating a STOP condition or

transmitting up to six more bytes of data and then

terminating by generating a STOP condition.

After this STOP condition, the E/W cycle starts and the bus

is free for another transmission. The duration of the

E/W cycle is 10 ms per byte.

During the E/W cycle, the slave receiver does not send an

acknowledge bit if addressed via the I2C-bus.

8.4.2

PAGE WRITE

The PCF8510xC-2 is capable of an 8-byte page write

operation. It is initiated in the same manner as the byte

write operation. The master can transmit eight data bytes

within one transmission. After receipt of each byte, the

PCF8510xC-2 will respond with an acknowledge.

The typical E/W time in this mode is 9

× 3.5 ms = 31.5 ms.

Erasing a block of eight bytes in page mode takes a typical

3.5 ms and sequential writing of these eight bytes another

typical 28 ms.

After the receipt of each data byte, the three low order bits

of the word address are internally incremented. The five

high order bits of the address remain unchanged.

The slave acknowledges the reception of each data byte

with an ACK. The I2C-bus data transfer is terminated by

the master after the eighth byte with a STOP condition.

If the master transmits more than eight bytes prior to

generating the STOP condition, no acknowledge will be

given on the ninth (and following) data bytes. Also, the

whole transmission will be ignored and no programming

will be done. As in the byte write operation, all inputs are

disabled until completion of the internal write cycles.

handbook, halfpage

MBC793

101

A0 R/W

Fig.4 Slave address for PCF85102C-2.

handbook, halfpage

MGL970

001

A0 R/W

Fig.5 Slave address for PCF85103C-2.

PCF85103C-2 Datasheet(PDF) 8 Page - NXP Semiconductors

PCF85103C-2 Datasheet(HTML) 8 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Descarga

Enlace URL