ST92F124 datasheet(252/429 Pages) STMICROELECTRONICS

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SERIAL PERIPHERAL INTERFACE (SPI)

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.7.4 Functional Description

Figure 121 shows the serial peripheral interface

(SPI) block diagram.

This interface contains 4 dedicated registers:

– A Control Register (SPCR)

– A Prescaler Register (SPPR)

– A Status Register (SPSR)

– A Data Register (SPDR)

Refer to the SPCR, SPPR, SPSR and SPDR reg-

isters in Section 10.7.6for the bit definitions.

10.7.4.1 Master Configuration

In a master configuration, the serial clock is gener-

ated on the SCK pin.

Procedure

– Define the serial clock baud rate by setting/re-

setting the DIV2 bit of SPPR register, by writ-

ing a prescaler value in the SPPR register and

programming the SPR0 & SPR1 bits in the

SPCR register.

– Select the CPOL and CPHA bits to define one

of the four relationships between the data

transfer and the serial clock (see Figure 123).

–The SS pin must be connected to a high level

signal during the complete byte transmit se-

quence.

– The MSTR and SPOE bits must be set (they

remain set only if the SS pin is connected to a

high level signal).

In this configuration the MOSI pin is a data output

and the MISO pin is a data input.

Transmit Sequence

The transmit sequence begins when a byte is writ-

ten the SPDR register.

The data byte is parallel loaded into the 8-bit shift

and then shifted out serially to the MOSI pin most

significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt is generated if the SPIS and SPIE

bits are set.

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the SPDR register is

read, the SPI peripheral returns this buffered val-

ue.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SPSR register while the SPIF

bit is set

2. A read of the SPDR register.

Note: While the SPIF bit is set, all writes to the

SPDR register are inhibited until the SPSR regis-

ter is read.

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