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ST92F124 Datasheet(PDF) 249 Page - STMicroelectronics |
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ST92F124 Datasheet(HTML) 249 Page - STMicroelectronics |
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249 / 429 page  249/429 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) R245 - Read/Write Register Page: 26 Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. Bits 7:1 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 119) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended Baud Rate Generator is not used af- ter a reset. EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIETPR) R246 - Read/Write Register Page: 26 Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate divi- sion factor for the transmit circuit. Bits 7:1 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 119) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended Baud Rate Generator is not used af- ter a reset. 10.6.6 Important Notes on SCI-A Refer to Section 13.4 on page 413 and Section 13.5 on page 413. 70 ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0 70 ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0 9 |
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