DRAM

DRAM

DRAM

DRAM

DRAM

AS4LC4M16

Austin Semiconductor, Inc.

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

23

AS4LC4M16

Rev. 1.0 7/02

SELF REFRESH CYCLE

(Addresses and OE\ = DON’T CARE)

NOTES:

1. Once t

RASS

(MIN) is met and RAS\ remains LOW, the DRAM will enter self refresh mode.

2. Once t

RPS

is satisfied, a complete burst of all rows should be executed if RAS\-only or burst CBR refresh is used.