P82C150AHT datasheet(24/36 Pages) PHILIPS

24 / 36 page

1996 Jun 19

Philips Semiconductors

Preliminary speciﬁcation

CAN Serial Linked I/O device (SLIO) with

digital and analog port functions

P82C150

Notes to the DC characteristics:

1. Alteration of VDD between two calibration messages should not exceed 0.2 V to avoid failures during CAN

message transfer. If CAN devices according to CAN specification V1.0 or V1.1 (like the 82C200 V0 or V1) are in the

same network with the 82C150, then this alteration of VDD should be limited to 0.1V for the 82C150.

2. These values are characterized but not 100% production tested.

3. The TX0 output pin is an open drain pull-down driver (no pull-up driver included).

4. The TX1 output pin is an open drain pull-up driver (no pull-down driver included).

10 AC CHARACTERISTICS

VDD =5V ± 4%; VSS =0V; CL = 100 pF (output pins); Tamb = −40 to +85 °C and Tamb = −40 to +125 °C; unless

otherwise speciﬁed.

Notes

1. Other bit time values are possible with the external oscillator mode (refer to Chapter 11.3).

2. These values are characterized but not 100% production tested.

OC1 comparator input P15

Vi sw

input switch-over voltage

1.5 V < VI <(AVDD − 1.5 V);

note 2

lower threshold

0.5VDD − 0.02

upper threshold

−

0.5VDD + 0.02

ILI2

input leakage current

0.45 V < VI <VDD − 0.45 V

−±400

CIA

analog input capacitance

note 2

−

Analog switches; ION =

±4mA

RON

On resistance

between P5 to P9, P13 and

P14; note 2

200

Ω

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

fCLK_INT

system clock frequency on-chip

internal oscillator

MHz

tbit

bit time on CAN-bus

note 1

µs

tRST1

min. RST pulse width after power on

note 2

150

−

tRST2

min. RST pulse width during operation

note 2

−µs

thold

ID hold time after end of reset

note 2

100

−

total signal delay of CAN input comparator and

CAN output driver

0.3AVDD <VI < 0.7AVDD;

note 2

−

100

trep

max. time without recalibration message

−

8000

bit

Analog-to-digital comparator input P15

tcyc

analog-to-digital conversion cycle time

0.4

1.1

tinit

initialization time of analog-to-digital conversion

0.4

2.1

OC2 comparator P12, P13 and OC3 comparator P10, P11

tresp

response time

VDIF1 = ±100 mV; note 2

µs

DPM1 and DPM2 outputs

tDPM

repetition time of DPM cycle

0.4

1.1

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

P82C150AHT Datasheet(PDF) 24 Page - NXP Semiconductors

P82C150AHT Datasheet(HTML) 24 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL