M750000005 datasheet(83/129 Pages) SPANSION

83 / 129 page

January 14, 2004

Am75PDL191CHHa/Am75PDL193CHHa

ADV ANCE

I N FO RMAT I O N

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

CC5 in the DC Characteristics table represents the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

SS±0.3 V, the device

draws CMOS standby current (I

CC4). If RESET# is held

at V

IL but not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t

READY (during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t

READY (not during Embedded Algo-

rithms). The system can read data t

RH after the RE-

SET# pin returns to V

IH.

Refer to the pSRAM AC Characteristics tables for RE-

SET# parameters and to Figure 15 for the timing dia-

gram.

Output Disable Mode

When the OE# input is at V

IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2.

Am29DL640H Sector Architecture

Bank

Sector

Sector Address

A21–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank 1

SA0

0000000000

00000h–00FFFh

SA1

0000000001

01000h–01FFFh

SA2

0000000010

02000h–02FFFh

SA3

0000000011

03000h–03FFFh

SA4

0000000100

04000h–04FFFh

SA5

0000000101

05000h–05FFFh

SA6

0000000110

06000h–06FFFh

SA7

0000000111

07000h–07FFFh

SA8

0000001xxx

08000h–0FFFFh

SA9

0000010xxx

10000h–17FFFh

SA10

0000011xxx

18000h–1FFFFh

SA11

0000100xxx

20000h–27FFFh

SA12

0000101xxx

28000h–2FFFFh

SA13

0000110xxx

30000h–37FFFh

SA14

0000111xxx

38000h–3FFFFh

SA15

0001000xxx

40000h–47FFFh

SA16

0001001xxx

48000h–4FFFFh

SA17

0001010xxx

50000h–57FFFh

SA18

0001011xxx

58000h–5FFFFh

SA19

0001100xxx

60000h–67FFFh

SA20

0001101xxx

68000h–6FFFFh

SA21

0001101xxx

70000h–77FFFh

SA22

0001111xxx

78000h–7FFFFh

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