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M700000002 Datasheet(PDF) 80 Page - SPANSION

No. de pieza M700000002
Descripción Electrónicos  2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
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M700000002 Datasheet(HTML) 80 Page - SPANSION

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78
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
AD VAN C E
INFORM ATION
pSRAM ADDRESS SKEW
Figure 30.
Read Address Skew
Note: If multiple invalid address cycles shorter than t
RC min occur for a period greater than 10 µs, at least one valid address cycle
over t
RC min is required during that period.
Figure 31.
Write Address Skew
Note: If multiple invalid address cycles shorter than t
WC min occur for a period greater than 10 µs, at least one valid address
cycle over t
WC min, in addition to tWP min, is required during that period.
CE#1ps
WE#
Address
tRC min
over 10
µs
CE#1ps
WE#
Address
tWP min
tWC min
over 10
µs



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