L160DT90VC datasheet(13/52 Pages) AMD

13 / 52 page

22358B7 May 5, 2006

Am29LV160D

DA TA

SH EET

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

system drives the RESET# pin to VIL for at least a pe-

riod of tRP, the device immediately terminates any

operation in progress, tristates all data output pins,

and ignores all read/write attempts for the duration of

the RESET# pulse. The device also resets the internal

state machine to reading array data. The operation

that was interrupted should be reinitiated once the de-

vice is ready to accept another command sequence,

to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is

held at VIL but not within VSS±0.3 V, the standby cur-

rent will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to deter mine

whether the reset operation is complete. If RESET#

is asserted when a program or erase operation is not

executing (RY/BY# pin is “1”), the reset operation is

completed within a time of tREADY (not during Embed-

ded Algorithms). The system can read data tRH after

the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high im-

pedance state.

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