AT89C51CC03CA-RDTZM datasheet(9/197 Pages) ATMEL

9 / 197 page

AT89C51CC03

4182K–CAN–05/06

Figure 1. Port 1, Port 3 and Port 4 Structure

Note:

The internal pull-up can be disabled on P1 when analog function is selected.

Port 0 and Port 2

Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port

0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3

shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to

turn off the output driver FET.

Figure 2. Port 0 Structure

Notes:

1. Port 0 is precluded from use as general-purpose I/O Ports when used as

address/data bus drivers.

2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only.

Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

P1.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

P1.x

P3.X

P4.X

ALTERNATE

OUTPUT

FUNCTION

VCC

INTERNAL

PULL-UP (1)

ALTERNATE

INPUT

FUNCTION

P3.x

P4.x

BUS

P0.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

P0.x (1)

ADDRESS LOW/

DATA

CONTROL

VDD

BUS

(2)

AT89C51CC03CA-RDTZM Datasheet(PDF) 9 Page - ATMEL Corporation

AT89C51CC03CA-RDTZM Datasheet(HTML) 9 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL