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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AT83SND1CXXX-ROTUL Datasheet(PDF) 14 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTUL Datasheet(HTML) 14 Page - ATMEL Corporation |
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14 / 212 page  14 4109J–8051–10/06 AT8xC51SND1C Figure 5-4. PLL Block Diagram and Symbol Figure 5-5. PLL Filter Connection 5.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 5-6. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. The PLL clock frequency will depend on MP3 decoder clock and audio interface clock frequencies. Figure 5-6. PLL Programming Flow PLLEN PLLCON.1 N6:0 N divider R divider VCO PLLclk OSCclk R 1 + () × N1 + ----------------------------------------------- = OSC CLOCK PFLD PLOCK PLLCON.0 PFILT CHP Vref Up Down R9:0 PLL CLOCK PLL Clock Symbol PLL Clock VSS FILT R C1 C2 VSS PLL Programming Configure Dividers N6:0 = xxxxxxb R9:0 = xxxxxxxxxxb Enable PLL PLLRES = 0 PLLEN = 1 PLL Locked? PLOCK = 1? |
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