ATMEGA161 datasheet(21/159 Pages) ATMEL

21 / 159 page

ATmega161(L)

1228D–AVR–02/07

All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions transferring data between the 32 general pur-

pose working registers and the I/O space. I/O Registers within the address range $00 -

$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as

SRAM, $20 must be added to this address. All I/O Register addresses throughout this

document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, thus clearing the Flag. The CBI and SBI instructions work with reg-

isters $00 to $1F only.

The I/O and Peripherals Control Registers are explained in the following sections.

Status Register – SREG

The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

•Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the

Global Interrupt Enable bit is cleared (zero), none of the interrupts are enabled indepen-

dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an

interrupt has occurred and is set by the RETI instruction to enable subsequent

interrupts.

•Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the Register File can be cop-

ied into T by the BST instruction and a bit in T can be copied into a bit in a register in the

•Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the

Instruction Set description for detailed information.

•Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-

ment Overflow Flag V. See the Instruction Set description for detailed information.

•Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See

the Instruction Set Description for detailed information.

Bit

543

210

$3F ($5F)

SREG

Read/Write

R/W

Initial Value

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