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AMC130M02DFMR Datasheet(PDF) 33 Page - Texas Instruments |
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AMC130M02DFMR Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 88 page  POR sequence DVDD supply present? Yes No No Yes DRDY high? Configure registers: CLK_DIV[1:0] DCDC_FREQ[3:0] All other configurations as needed Set DCDC_EN = 1b No Yes External clock provided at CLKIN pin? Send NULL command or RREG command to read from STATUS register No Yes SEC_FAIL status bit is low? Power supply DVDD on primary (low) side not valid Power supply HLDO_OUT on secondary (high) side not valid ADC is generating conversion data No Yes DRDY pin or DRDY status bit is low? ADC conversion is ongoing New, valid conversion data is available to read via SPI DVDD supply present? No Yes Power down Device is still powered Device was powered down No Yes Digital filter is settled? ADC data is not settled Figure 8-17. Flow Diagram for Start-Up Procedure at Power-Up www.ti.com AMC130M02 SBASAN9 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: AMC130M02 |
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