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WM8593 Datasheet(PDF) 14 Page - Wolfson Microelectronics plc |
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WM8593 Datasheet(HTML) 14 Page - Wolfson Microelectronics plc |
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14 / 98 page  WM8593 Product Preview w PP Rev 1.0 January 2007 14 CONTROL INTERFACE TIMING – 2-WIRE MODE Figure 4 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25˚C, Slave Mode, fs = 48kHz, ADCMCLK, DACMCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK pulse cycle time tSCY 2500 ns SCLK duty cycle 40/60 60/40 % SCLK frequency 400 kHz Hold Time (Start Condition) tSTHO 600 ns Setup Time (Start Condition) tSTSU 600 ns Data Setup Time tDSU 100 ns SDIN, SCLK Rise Time 300 ns SDIN, SCLK Fall Time 300 ns Setup Time (Stop Condition) tSTOP 600 ns Data Hold Time tDHO 900 ns Pulse width of spikes that will be suppressed tps 2 8 ns Table 4 Control Interface Timing – 2-Wire Serial Control Mode SDIN SCLK t STHO t SCY t DSU t STSU t STHO t STOP t DH |
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