WM8150SCDSSLASHR datasheet(14/26 Pages) WOLFSON

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WM8150

Production Data

PD Rev 4.1 February 2005

VVRLC

(VRLCSTEP

∗ RLCV[3:0]) + VRLCBOT ................................. Eqn. 3

VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

The resultant signal V1 is added to the Offset DAC output.

V1 + {260mV

∗ (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain,

∗ [0.78+(PGA[7:0]*7.57)/255] ................................... Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 12-bit unsigned number, with input range configured by

PGAFS[1:0].

D1[11:0] = INT{ (V3 /VFS)

∗ 4095} + 2047

PGAFS[1:0] = 00 or 01 ......

Eqn. 6

D1[11:0] = INT{ (V3 /VFS)

∗ 4095}

PGAFS[1:0] = 11 ...............

Eqn. 7

D1[11:0] = INT{ (V3 /VFS)

∗ 4095} + 4095

PGAFS[1:0] = 10 ...............

Eqn. 8

where the ADC full-scale range, VFS = 2.5V

if D1[11:0] < 0

D1[11:0] = 0

if D1[11:0] > 4095

D1[11:0] = 4095

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

D2[11:0] = D1[11:0]

(INVOP = 0) ......................

Eqn. 9

D2[11:0] = 4095 – D1[11:0]

(INVOP = 1) ......................

Eqn. 10

WM8150SCDS/R Datasheet(PDF) 14 Page - Wolfson Microelectronics plc

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