CAT25C64LSATE13 datasheet(9/11 Pages) CATALYST

No. de pieza	CAT25C64LSATE13

Descripción Electrónicos	32K/64K-Bit SPI Serial CMOS EEPROM

PDF	11 Pages

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Fabricante Electrónico	CATALYST [Catalyst Semiconductor]

Página de inicio	http://www.catalyst-semiconductor.com

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CAT25C32/64

Doc. No. 1001, Rev. G

Figure 9.

HOLD

HOLD Timing

Figure 8. Page Write Instruction Timing

Note: Dashed Line = mode (1, 1) – – – –

Note: Dashed Line= mode (1, 1) — — — —

ADDRESS

Data

Byte 1

012345678

23 24-31

32-39

Data

Byte 2

Data

Byte 3

Data Byte N

OPCODE

7..1

24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1

DATA IN

HIGH IMPEDANCE

SCK

HOLD

tCD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE

proper number of clock cycles to start an internal write

cycle. Access to the array during an internal write cycle

is ignored and program-ming is continued. On power up,

SO is in a high impedance.

When powering down, the supply should be taken down

to 0V, so that the CAT25C32/64 will be reset when

power is ramped back up. If this is not possible, then,

following a brown-out episode, the CAT25C32/64 can

be reset by refreshing the contents of the Status Regis-

ter (See Application Note AN10).

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