Philips Semiconductors

Product specification

Silicon Diffused Power Transistor

BUT11AF

Fig.3. Test circuit resistive load. V

V

R

Fig.4. Switching times waveforms with resistive load.

Fig.5. Test circuit inductive load.

V

Fig.6. Switching times waveforms with inductive load.

Fig.7. Normalised power derating and second

breakdown curves.

Fig.8. Reverse bias safe operating area. T

tp

T

VCC

R

R

T.U.T.

0

VIM

B

L

IC

IB

ICon

IBon

-IBoff

t

t

ts

tf

toff

10 %

90 %

0

20

40

60

80

100

120

140

Ths / C

%

Normalised Derating

120

110

100

90

80

70

60

50

40

30

20

10

0

with heatsink compound

P tot

IC

IB

10 %

10 %

90 %

90 %

ton

toff

ts

tf

IBon

-IBoff

ICon

tr

30ns

6

5

4

3

2

1

0

0

400

800

1200

IC / A

BUT11AX

VCE / V

LB

IBon

-VBB

LC

T.U.T.

VCC

August 1997

3

Rev 1.000