AT80C51RA2-3CSCL datasheet(13/85 Pages) IRF

13 / 85 page

4188E–8051–08/06

AT/TS8xC51Rx2

Figure 5-1.

Clock Generation Diagram

Figure 5-2.

Mode Switching Waveforms

The X2 bit in the CKCON register (Table 5-2) allows to switch from 12 clock cycles per instruc-

tion to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode).

Setting this bit activates the X2 feature (X2 mode).

Note:

In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all

peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time ref-

erence divided by two. For example a free running timer generating an interrupt every 20 ms will

then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.

Table 5-2.

CKCON Register

CKCON - Clock Control Register (8Fh)

XTAL1

CKCON reg

state machine: 6 clock cycles.

CPU control

FOSC

FXTAL

XTAL1:2

XTAL1

CPU clock

X2 bit

X2 Mode

STD Mode

543

210

---

Bit Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

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