ES9080 datasheet(87/146 Pages) ESS

87 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

ES9080 Product Datasheet

Bits

[7:5]

[4]

[3]

[2]

[1]

[0]

Default

3'd0

1'b0

Bits

Mnemonic

Description

[7:5]

RESERVED

[4]

SYNC_DAC_CLK_DIV

Controls clock divider reset on negative edge of WS.

•

1’b1: Clock divider will be reset at every negative edge

of WS

•

1’b0: Disable the FIR_RESYNC reset

Note: If reset the SYNC_DAC_CLK_DIV (ie 1’b1), toggle this

bit before setting any other RESYNC bits [3:0]

[3]

DOP_CLK_RESYNC

Controls Dop clock divider reset on negative edge of WS.

•

1’b1: Clock divider will be reset at every negative edge

of WS

•

1’b0: Disable the FIR_RESYNC reset

[2]

VOL_THD_RESYNC

Controls Volume-THD block reset on negative edge of WS.

•

1’b1: DoP clock generator will be reset at every

negative edge of WS

•

1’b0: Disable the DOP_CLK_RESYNC reset

[1]

FIR_RESYNC

Controls FIR filters reset on negative edge of WS.

•

1’b1: FIR filters will be reset at every negative edge of

•

1’b0: Disable the FIR_RESYNC reset

[0]

FS_RESYNC

Controls FS clock generator reset on negative edge of WS.

•

1’b1: FS clock generator will be reset at every

negative edge of WS

•

1’b0: Disable the FS_RESYNC reset

Bits

[7:0]

Default

8'd0

Bits

Mnemonic

Description

[7:0]

VOLUME1

DAC ch1 volume. -0dB to -127.5dB 0.5dB steps.

•

8'd0: 0dB

•

8'd255: -127.5 dB

ES9080 Datasheet(PDF) 87 Page - ESS Technology,Inc

ES9080 Datasheet(HTML) 87 Page - ESS Technology,Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL