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ES9028Q2M Datasheet(PDF) 18 Page - ESS Technology,Inc

No. de pieza ES9028Q2M
Descripción Electrónicos  32-Bit Stereo Low Power Audio DAC
PDF  45 Pages
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Fabricante Electrónico  ESS [ESS Technology,Inc]
Página de inicio  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9028Q2M Datasheet(HTML) 18 Page - ESS Technology,Inc

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January 16, 2020
ES9028Q2M Datasheet
ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-
8800 • WWW.ESSTECH.COM
18
Register #11: Channel Mapping
8 bit, Read-Write Register, Default = 0x02
Bits
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Mnemonic
reserved *
spdif_sel
ch2_analog_swap
ch1_analog_swap
ch2_sel
ch1_sel
Default
0
0
0
0
0
0
1
0
Bit
Mnemonic
Description
[7]
reserved *
[6:4]
spdif_sel
select the spdif data source
3’d0 = DATA_CLK (default)
3’d1 = DATA2
3’d2 = DATA1
3’d3 = GPIO1
3’d4 = GPIO2
3’d5-7: reserved
[3]
ch2_analog_swap
1
’b0 = normal operation (default)
1
’b1 = swap dac and dacb
[2]
ch1_analog_swap
1
’b0 = normal operation (default)
1
’b1 = swap dac and dacb
[1]
ch2_sel
1
’b0 = left
1
’b1 = right (default)
[0]
ch1_sel
1
’b0 = left (default)
1
’b1 = right
* All Reserved Bits in Register #11 must be set to the indicated logic level to ensure correct device operation.
Left and Right channels can be reversed using Register #11.



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