NB650/NB650H

– 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS

NB650/NB650H Rev. 1.13

www.MonolithicPower.com

10

10/7/2019

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Preliminary Specifications Subject to Change

© 2019 MPS. All Rights Reserved.

following equation determines the critical level of

the output current:

IN

OUT

OUT

OUT

SW

IN

(V

V

) V

I

2 L f

V





 



(2)

When the output current exceeds the critical

level, light load mode turns into PWM mode, and

the switching frequency stays fairly constant over

the output current range.

Switching Frequency

The

NB650/NB650H

uses

constant-on-time

(COT) control, and has no dedicated internal

oscillator. The input voltage is feed-forwarded to

the on-time one-shot timer through the resistor

RFREQ. The duty ratio is kept as VOUT/VIN. Hence,

the switching frequency is fairly constant over the

input voltage range. The switching frequency can

be set as follows:

6

1

2

1

10

4

0

6

9



























































)

ns

(

t

)

V

(

V

)

V

(

V

)

ns

(

t

.

)

V

(

V

)

k

(

R

.

)

kHz

(

f

DELAY

OUT

IN

DELAY

IN

FREQ

SW

(3)

Where tDELAY2 is another comparator delay of

about 40ns.

Figure 4: Plot of VOUT as a Function of RFREQ and

the Frequency

NB650/NB650H is optimized to operate at high

switching frequencies at high efficiency. Higher

switching frequencies allow for smaller LC filter

components to reduce system PCB space.

Jitter and FB Ramp Slope

Figure 5 and Figure 6 show jitter in both PWM

and skip modes. When there is noise in the VFB

downward slope, the ON time of

HS-FET

deviates from its intended level and produces

jitter. There

is a relationship between a system’s

stability and the steepness of the VFB ripple’s

downward slope: The steepness of the VFB

ripple

’s slope dominates in noise immunity. The

magnitude of the VFB ripple doesn’t directly affect

the noise immunity.

Figure 5: Jitter in PWM Mode

Figure 6: Jitter in Skip Mode

Ramp with Large ESR Cap

When

using

POSCAPs

or

other

types

of

capacitors with larger ESR as output capacitors.

the ESR ripple dominates the output ripple, and

the slope on the FB is ESR-related. Figure 7

shows an equivalent circuit in PWM mode with

the HS-FET off and without an external ramp

circuit. The application section includes design

steps for large ESR capacitors.