WM8721SEDSSLASHR datasheet(26/37 Pages) WOLFSON

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WM8721 / WM8721L

Production Data

PD Rev 4.0 November 2004

2-WIRE SERIAL CONTROL MODE

The WM8721 supports a 2-wire MPU serial interface. The device operates as a slave device only.

The WM8721 has one of two slave addresses that are selected by setting the state of pin 15 (SSOP)

/ 26 (QFN), (CSB).

SDIN

SCLK

ACK

R ADDR

ACK

DATA B15-8

STOP

START

DATA B7-0

R/W

ACK

Figure 19 2-Wire Serial Interface

Notes:

B[15:9] are Control Address Bits

B[8:0] are Control Data Bits

CSB STATE

Address

0011010

0011011

Table 17 2-Wire MPU Interface Address Selection

To control the WM8721 on the 2-wire bus the master control device must initiate a data transfer by

establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.

This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond

to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB

first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of

two available addresses for this device (see Table 17). If the correct address is received and the R/W

bit is ‘0’, indicating a write, then the WM8721 will respond by pulling SDIN low on the next clock pulse

(ACK). The WM8721 is a write only device and will only respond to the R/W bit indicating a write. If

the address is not recognised the device will return to the idle condition and wait for a new start

condition and valid address.

Once the WM8721 has acknowledged a correct address, the controller will send eight data bits (bits

B15-B8). WM8721 will then acknowledge the sent data by pulling SDIN low for one clock pulse. The

controller will then send the remaining eight data bits (bits B7-B0) and the WM8721 will then

acknowledge again by pulling SDIN low.

A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a

start or stop condition is detected out of sequence at any point in the data transfer then the device

will jump to the idle condition.

After receiving a complete address and data sequence the WM8721 returns to the idle state and

waits for another start condition. Each write to a register requires the complete sequence of start

condition, device address and R/W bit followed by the 16 register address and data bits.

WM8721SEDS/R Datasheet(PDF) 26 Page - Wolfson Microelectronics plc

WM8721SEDS/R Datasheet(HTML) 26 Page - Wolfson Microelectronics plc

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