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UPD17062 Datasheet(PDF) 225 Page - Renesas Technology Corp

No. de pieza UPD17062
Descripción Electrónicos  MOS INTEGRATED CIRCUIT
PDF  298 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
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UPD17062 Datasheet(HTML) 225 Page - Renesas Technology Corp

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µPD17062
18.4
REFERENCE FREQUENCY GENERATOR (RFG)
18.4.1
Reference Frequency Generator (RFG) Configuration and Functions
Fig. 18-3 shows the configuration of the reference frequency generator.
As shown in Fig. 18-3, the reference frequency generator divides the frequency of the clock oscillator (8
MHz) to generate the reference frequency “fr” for the PLL frequency synthesizer.
The reference frequency fr can be selected from 6.25, 12.5, and 25 kHz.
Selection of the reference frequency fr is performed using the PLL reference mode select register (at address
13H).
Section 18.4.2 describes the configuration and functions of the PLL reference mode select register.
Fig. 18-3
Reference Frequency Generator (RFG) Configuration
13H
b3
b2
b0
b1
P
L
L
R
F
C
K
3
P
L
L
R
F
C
K
2
P
L
L
R
F
C
K
0
P
L
L
R
F
C
K
1
8 MHz
6.25 kHz
12.5 kHz
25 kHz
OFF
Control register
Address
Bit
Flag
symbol
Multiplexer
PLL disable signal
To
-DET
φ
Divider



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