UPD17062 datasheet(224/298 Pages) RENESAS

No. de pieza	UPD17062

Descripción Electrónicos	MOS INTEGRATED CIRCUIT

PDF	298 Pages

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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µPD17062

18.3.2

Programmable Divider (PD) and Data Buffer (DBF)

The programmable divider divides the frequency of an input signal at the VCO pin by the values specified

in the swallow counter and programmable counter.

The swallow and programmable counters consist of a 4- and 12-bit binary downcounter, respectively.

The swallow and programmable counters are loaded with a division value by setting it in the PLL data

Writing to and reading from the PLL data register are performed with the “PUT PLLR,DBF” and “GET

DBF,PLLR” instructions respectively.

A division value is called an N-value.

The following expression represents the frequency “fN” of a signal generated in the programmable divider

using the value N in the PLL data register (PLLR).

Pulse swallow method

fN =

fin

(where N is 16 bits)

See Section 18.7 for how to set the division value (N-value) for each frequency division method.

UPD17062 Datasheet(PDF) 224 Page - Renesas Technology Corp