ST72340 datasheet(106/191 Pages) STMICROELECTRONICS

106 / 191 page

ST72340, ST72344, ST72345

106/191

SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.4.7 Parity control

Parity control (generation of parity bit in transmis-

sion and parity checking in reception) can be ena-

bled by setting the PCE bit in the SCICR1 register.

Depending on the frame length defined by the M

bit, the possible SCI frame formats are as listed in

Table 1.

Table 21. Frame Formats

Legend:

SB: Start Bit

STB: Stop Bit

PB: Parity Bit

Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not

the parity bit

Even parity: The parity bit is calculated to obtain

an even number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit

is 0 if even parity is selected (PS bit = 0).

Odd parity: The parity bit is calculated to obtain

an odd number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit

is 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

(PS = 0) or an odd number of “1s” if odd parity is

selected (PS = 1). If the parity check fails, the PE

flag is set in the SCISR register and an interrupt is

generated if PIE is set in the SCICR1 register.

11.5.4.8 SCI Clock Tolerance

During reception, each bit is sampled 16 times.

The majority of the 8th, 9th and 10th samples is

considered as the bit value. For a valid bit detec-

tion, all the three samples should have the same

value otherwise the noise flag (NF) is set. For ex-

ample: if the 8th, 9th and 10th samples are 0, 1

and 1 respectively, then the bit value is “1”, but the

Noise Flag bit is set because the three samples

values are not the same.

Consequently, the bit length must be long enough

so that the 8th, 9th and 10th samples have the de-

sired bit value. This means the clock frequency

should not vary more than 6/16 (37.5%) within one

bit. The sampling clock is resynchronized at each

start bit, so that when receiving 10 bits (one start

bit, 1 data byte, 1 stop bit), the clock deviation

must not exceed 3.75%.

Note: The internal sampling clock of the microcon-

troller samples the pin value on every falling edge.

Therefore, the internal sampling clock and the time

the application expects the sampling to take place

may be out of sync. For example: If the baud rate

is 15.625 kbaud (bit length is 64µs), then the 8th,

9th and 10th samples will be at 28µs, 32µs and

36µs respectively (the first sample starting ideally

at 0µs). But if the falling edge of the internal clock

occurs just before the pin value changes, the sam-

ples would then be out of sync by ~4us. This

means the entire bit length must be at least 40µs

(36µs for the 10th sample + 4µs for synchroniza-

tion with the internal sampling clock).

M bit

PCE bit

SCI frame

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data PB | STB |

ST72340 Datasheet(PDF) 106 Page - STMicroelectronics

ST72340 Datasheet(HTML) 106 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL