ST72340 datasheet(58/191 Pages) STMICROELECTRONICS

58 / 191 page

ST72340, ST72344, ST72345

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11 ON-CHIP PERIPHERALS

11.1 WINDOW WATCHDOG (WWDG)

11.1.1 Introduction

The Window Watchdog is used to detect the oc-

currence of a software fault, usually generated by

external interference or by unforeseen logical con-

ditions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the contents of the downcounter before the T6

bit becomes cleared. An MCU reset is also gener-

ated if the 7-bit downcounter value (in the control

reached the window register value. This implies

that the counter must be refreshed in a limited win-

dow.

11.1.2 Main Features

■ Programmable free-running downcounter

■ Conditional reset

– Reset (if watchdog activated) when the down-

counter value becomes less than 40h

– Reset (if watchdog activated) if the down-

counter is reloaded outside the window (see

Figure 4)

■ Hardware/Software

Watchdog

activation

(selectable by option byte)

■ Optional

reset

HALT

instruction

(configurable by option byte)

11.1.3 Functional Description

The counter value stored in the WDGCR register

(bits T[6:0]), is decremented every 16384 fOSC2

cycles (approx.), and the length of the timeout pe-

riod can be programmed by the user in 64 incre-

ments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit downcounter (T[6:0] bits) rolls

over from 40h to 3Fh (T6 becomes cleared), it ini-

tiates a reset cycle pulling low the reset pin for typ-

ically 30

µs. If the software reloads the counter

while the counter is greater than the value stored

in the window register, then a reset is generated.

Figure 37. Watchdog Block Diagram

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

WATCHDOG CONTROL REGISTER (WDGCR)

WATCHDOG WINDOW REGISTER (WDGWR)

comparator

T6:0 > W6:0

CMP

= 1 when

Write WDGCR

WDG PRESCALER

DIV 4

fOSC2

12-BIT MCC

RTC COUNTER

MSB

LSB

DIV 64

MCC/RTC

TB[1:0] bits

(MCCSR

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