UPD6P9 datasheet(15/73 Pages) RENESAS

15 / 73 page

µPD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

2.9 Flags

2.9.1 Status flag (F)

Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.

The status flag is set (to 1) in the following cases.

• If the condition specified with the operand is met when the STTS instruction is executed

• When standby mode is released.

• When the release condition is met at the point of executing the HALT instruction.

(In this case, the system

does not enter the standby mode.)

Conversely, the status flag is cleared (to 0) in the following cases:

• If the condition specified with the operand is not met when the STTS instruction is executed.

• When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met

at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.)

Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction

Operand Value of STTS Instruction

Condition for Status Flag (F) to Be Set

0000

High level is input to at least one of KI pins.

011

High level is input to at least one of KI pins.

110

High level is input to at least one of KI pins.

101

The down counter of the timer is 0.

Either of the combinations

[The following condition is added in addition to the above.]

of b2, b1, and b0 above.

High level is input to at least one of S0Note 1, S1Note 1, or S2Note 2 pins.

Notes 1. The S0 and S1 pins must be set to input mode (bit 2 and bit 0 of the P4 register are set to 0 and 1,

respectively).

2. The use of STOP mode release for the S2 pin must be enabled (bit 3 of the P4 register is set to 1).

2.9.2 Carry flag (CY)

The carry flag is set (to 1) in the following cases:

• If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the

operand is 1.

• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 1.

• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH.

The carry flag is cleared (to 0) in the following cases:

• If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit

3 of the operand is 0.

• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 0.

• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH.

• If the ORL instruction is executed.

• When data is written to the accumulator by the MOV instruction or the IN instruction.

UPD6P9 Datasheet(PDF) 15 Page - Renesas Technology Corp

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