MCP621T datasheet(26/68 Pages) MICROCHIP

26 / 68 page

MCP621/1S/2/3/4/5/9

DS20002188E-page 26

 2009-2021 Microchip Technology Inc. and its subsidiaries

4.4

Improving Stability

4.4.1

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. See Figure 2-30. A unity gain buffer (G = +1)

is the most sensitive to capacitive loads, though all

gains show the same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 10 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-9) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-9:

Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Figure 4-10 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For noninverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN =+2V/V).

FIGURE 4-10:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO, double check the resulting fre-

quency response peaking and step response over-

shoot. Modify RISO’s value until the response is

reasonable. Bench evaluation and simulations with the

MCP621/1S/2/3/4/5/9 SPICE macro model are helpful.

4.4.2

GAIN PEAKING

Figure 4-11 shows an op amp circuit that represents

noninverting amplifiers (VM is a DC voltage and VP is

the input) or inverting amplifiers (VP is a DC voltage

and VM is the input). The capacitances CN and CG

represent the total capacitance at the input pins; they

include the op amp’s Common mode input capacitance

(CCM), board parasitic capacitance and any capacitor

placed in parallel.

FIGURE 4-11:

Amplifier with Parasitic

Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/

V), which causes an increase in gain at high

frequencies. CG also reduces the phase margin of the

feedback loop, which becomes less stable. This effect

can be reduced by either reducing CG or RF.

CN and RN form a low-pass filter that affects the signal

at VP. This filter has a single real pole at 1/(2RNCN).

The largest value of RF that should be used depends

on noise gain (see GN in Section 4.4.1 “Capacitive

Loads”) and CG. Figure 4-12 shows the maximum

recommended RF for several CG values.

FIGURE 4-12:

Maximum Recommended

RF vs. Gain.

Figures 2-37 and 2-38 show the small signal and large

signal step responses at G = +1 V/V. The unity gain

buffer usually has RF =0 and RG open.

Figures 2-39 and 2-40 show the small signal and large

signal step responses at G = -1 V/V. Since the noise

gain is 2 V/V and CG  10 pF, the resistors were

chosen to be RF =RG =1k and RN =500.

RISO

VOUT

MCP62X

100

1,000

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

Normalized Capacitance; CL/GN (F)

GN = +1

GN  +2

100p

10n

10p

VOUT

MCP62X

1.E+02

1.E+03

1.E+04

1.E+05

110

100

Noise Gain; GN (V/V)

GN > +1 V/V

100

10k

100k

CG = 10 pF

CG = 32 pF

CG = 100 pF

CG = 320 pF

CG = 1 nF

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