UPC1830 datasheet(21/46 Pages) RENESAS

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µPC1830

Figure 5-7. Sync. Separation Waveform

VS in Figure 5-7 represents the slice voltage and can be expressed in the following expression if it is assumed

that CO is sufficiently large, and both IX and ISP are linear.

VS = 2.5

× (RX/RO) × (T2/T1) [V]

The

µPC1830 amplifies the part lower than this slice voltage (VS) to perform sync. separation.

To determine sync. separation sensitivity, change RX to set VS. Decreasing VS is advantageous for separation

of the horizontal sync. part, but disadvantageous for separation of the vertical sync. part. On the contrary,

increasing VS may cause a sync. failure (jitter) due to noise (spikes) of the horizontal sync. part. Therefore, it

is necessary to optimize the constant in accordance with a signal input. As capacitance CO, select a sufficiently

large value compared with the charge/discharge current. However, an excessive value may deteriorate the

excessive response characteristic, failing to catch up with drastic APL variations of the input signal.

The larger RX, the larger the slice level becomes. However, with large RX if the sync. signal level drops (weak

electric field signal, etc.) a video signal may be confused with a sync. signal and sliced, making synchronization

unstable (abnormal).

Caution

Since the measuring circuit uses capacitor coupling for input for ease of measurement, it is

susceptible to APL variations. Therefore, when configuring the actual circuit, use a Sync Tip

clamp circuit in the stage prior to inputting to the emitter follower to stabilize the synchronization

peak potential and this will make the circuit more resistant to APL variations.

(3) Vertical filter circuit

Separates the vertical sync. signal from the sync. signal separated by the sync. separation circuit.

(4) Horizontal sync. detection circuit

Detects the presence of a horizontal sync. signal and changes the AFC time constant.

(5) AFC detection circuit

Performs phase detection on an input sync. signal and fH and outputs the phase difference in voltage.

Stops phase detection for 9H of the vertical blanking period.

(6) 32fH VCO

Controls VCO according to the voltage output by the AFC detection circuit and generates 32fH oscillation clocks.

T1 (4.7

T2 (58.86

Discharge by IX

Charge by ISP

UPC1830 Datasheet(PDF) 21 Page - Renesas Technology Corp