Nexperia

74HC2G02; 74HCT2G02

Dual 2-input NOR gate

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 10.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Input

Load

S1 position

Type

VI

tr, tf

CL

RL

tPHL, tPLH

74HC2G02

GND to VCC

≤ 6 ns

15 pF, 50 pF

1 kΩ

open

74HCT2G02

GND to 3 V

≤ 6 ns

15 pF, 50 pF

1 kΩ

open

74HC_HCT2G02

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2018. All rights reserved

Product data sheet

Rev. 6 — 26 July 2018

7 / 12