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M16C/62P Datasheet(PDF) 38 Page - Renesas Technology Corp |
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M16C/62P Datasheet(HTML) 38 Page - Renesas Technology Corp |
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38 / 87 page ![]() M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P) 4 8 f o 3 0 0 2 , 7 0 . v o N 0 1 . 2 . v e R page 38 VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified) Table 5.14 Memory Expansion Mode and Microprocessor Mode Max. External clock rise time ns tr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf Parameter Symbol Unit Standard 62.5 25 25 15 15 Table 5.13 External Clock Input (XIN input) (Note 1) (Note 2) (Note 3) 40 30 0 0 40 0 1. Calculated according to the BCLK frequency as follows: Min. Data input setup time ns tsu(DB-RD) tsu(RDY-BCLK ) Parameter Symbol Unit Max. Standard ns RDY input setup time Data input hold time ns th(RD-DB) th(BCLK -RDY) ns RDY input hold time ns HOLD input setup time tsu(HOLD-BCLK ) ns HOLD input hold time th(BCLK-HOLD ) Data input access time (for setting with no wait) ns tac1(RD-DB) ns ns tac2(RD-DB) tac3(RD-DB) Data input access time (for setting with wait) Data input access time (when accessing multiplex bus area) f(BCLK) – 45 0.5 X 109 [ns] 2. Calculated according to the BCLK frequency as follows: f(BCLK) – 45 (n–0.5) X 109 [ns] 3. Calculated according to the BCLK frequency as follows: f(BCLK) – 45 (n–0.5) X 109 [ns] n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting. n is “2” for 2-wait setting, “3” for 3-wait setting. NOTES: |
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