AD9927BBCZ datasheet(6/100 Pages) AD

6 / 100 page

AD9927

Rev. 0 | Page 6 of 100

TIMING SPECIFICATIONS

CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK (See Figure 16)

CLI Clock Period

tCONV

CLI High/Low Pulse Width

12.5

Delay from CLI Rising Edge to Internal Pixel Position 0

tCLIDLY

VD FALLING EDGE TO HD FALLING EDGE IN SLAVE MODE (See Figure 89)

tVDHD

VD period − 5 × tCONV

AFE CLPOB PULSE WIDTH (See Figure 23 and Figure 33)1, 2

Pixels

AFE SAMPLE LOCATION (See Figure 17 and Figure 20)1

SHP Sample Edge to SHD Sample Edge

tS1

12.5

DATA OUTPUTS (See Figure 21 and Figure 22)

Output Delay from DCLK Rising Edge

tOD

Inhibited Area for DOUTPHASE Edge Location

tDOUTINH

SHDLOC + 1

SHDLOC + 15

Edge

location

Pipeline Delay from SHP/SHD Sampling to DOUT

Cycles

SERIAL INTERFACE (See Figure 97)

Maximum SCK Frequency (Must Not Exceed CLI Frequency)

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Falling Edge to SDATA Valid Hold

tDH

1 Parameter is programmable.

2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

AD9927BBCZ Datasheet(PDF) 6 Page - Analog Devices

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