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Rev. 0 | Page 6 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A

87

6

54

32

1

B

C

D

E

F

G

H

BOTTOM VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

A1

VINA

Analog Input Pin (+) for Channel A.

A2

VINA

Analog Input Pin (−) for Channel A.

H1

VINB

Analog Input Pin (+) for Channel B.

H2

VINB

Analog Input Pin (−) for Channel B.

B4

CLK_A

Clock Input Pin for Channel A.

G4

CLK_B

Clock Input Pin for Channel B.

C4

PDWN_A

Power-Down Function Selection for Channel A (Active High).

F4

PDWN_B

Power-Down Function Selection for Channel B (Active High).

A4

OTR_A

Out-of-Range Indicator for Channel A.

E8

OTR_B

Out-of-Range Indicator for Channel B.

A3

VCM_A

Channel A Common Mode.

H3

VCM_B

Channel B Common Mode.

D4

OEB_A

Output Enable for Channel A. Logic 0 enables Data Bus A; Logic 1 sets outputs to high-Z.

E4

OEB_B

Output Enable for Channel B. Logic 0 enables Data Bus B; Logic 1 sets outputs to high-Z.

C5

D11_A(MSB)

Channel A Data Output Bit 11 (MSB).

A5

D10_A

Channel A Data Output Bit 10.

B5

D09_A

Channel A Data Output Bit 9.

A6

D08_A

Channel A Data Output Bit 8.

B6

D07_A

Channel A Data Output Bit 7.

A7

D06_A

Channel A Data Output Bit 6.

B7

D05_A

Channel A Data Output Bit 5.

A8

D04_A

Channel A Data Output Bit 4.

C6

D03_A

Channel A Data Output Bit 3.

B8

D02_A

Channel A Data Output Bit 2.

C7

D01_A

Channel A Data Output Bit 1.

C8

D00_A(LSB)

Channel A Data Output Bit 0 (LSB).

E3

DFS

Data Output Format Select Bit (Logic 0 for offset binary, Logic 1 for twos complement).

E7

D11_B(MSB)

Channel B Data Output Bit 11 (MSB).

F8

D10_B

Channel B Data Output Bit 10.

F7

D09_B

Channel B Data Output Bit 9.

G8

D08_B

Channel B Data Output Bit 8.