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VL6524 Datasheet(PDF) 30 Page - STMicroelectronics

No. de pieza VL6524
Descripción Electrónicos  VGA single-chip camera module
PDF  70 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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VL6524 Datasheet(HTML) 30 Page - STMicroelectronics

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Data synchronization methods
VL6524/VS6524
30/70
8.2.2
Vertical synchronization (VSYNC)
The VSYNC signal is controlled by the
bVSyncSetup register. The following options are
available:
●
enable/disable
●
select polarity
●
manual or automatic
In automatic mode the VSYNC signal envelops all the active video lines in the output frame
regardless of the programmed image size as shown in
Figure 16.
Figure 16.
VSYNC timing example
If manual mode is selected then the line number for VSYNC rising edge and falling edge is
programmable. The rising edge of VSYNC is programmed in the
bVsyncRisingLineH,
bVsyncRisingLineL registers, the pixel position for VSYNC rising edge is programmed in the
bVsyncRisingPixelH and bVsyncRisingPixelL registers. Similarly the line count for the falling
edge position is specified in the
bVsyncFallingLineH and bVsyncFallingLineL registers, and
the pixel count is specified in the
bVsyncFallingPixelH and bVsyncFallingPixelL registers
described in
Table 29: Output formatter control.
BLANKING
BLANKING
V=1
V=0
V=1
V=0
vsync
ACTIVE
VIDEO
ACTIVE
VIDEO



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