Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aae331

VEXT

VCC

VI

VO

DUT

CL

RT

RL

RL

G

Test data is given in Table 9.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig. 9. Test circuit for measuring switching times

Table 9. Test data

Input

Load

VEXT

Supply voltage

VI

tr, tf

CL

RL

tPLH, tPHL

tPLZ, tPZL

tPHZ, tPZH

1.2 V

VCC

≤ 2 ns

30 pF

1 kΩ

open

2 × VCC

GND

1.65 V to 1.95 V

VCC

≤ 2 ns

30 pF

1 kΩ

open

2 × VCC

GND

2.3 V to 2.7 V

VCC

≤ 2 ns

30 pF

500 Ω

open

2 × VCC

GND

2.7 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

2 × VCC

GND

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

2 × VCC

GND

74LVC_LVCH16374A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 13 — 27 September 2021

9 / 13