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SLG47502V Datasheet(PDF) 53 Page - Renesas Technology Corp

No. de pieza SLG47502V
Descripción Electrónicos  Low Voltage GreenPAK Programmable Mixed-Signal Matrix
PDF  192 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SLG47502V Datasheet(HTML) 53 Page - Renesas Technology Corp

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Datasheet
28-Feb-2023
CFR0011-120-00
Revision 2.3
53 of 194
© 2023 Renesas Electronics Corporation
SLG47512/13
Low Voltage GreenPAK Programmable
Mixed-Signal Matrix
Preliminary
Figure 28: 3-bit LUT7 or DFF10 or Shift Register 10
Figure 29: 3-bit LUT8 or DFF11 or Shift Register 11
3
8 memory cells
D_in
Clk
nSET/nRST
SET/RST
S1
S0
000
111
.
.
.
[7]
3-bit LUT
S0
S1
S1
S0
S0
S1
S0
S1
From Connectinon
Matrix Output [30]
3
ShRg/LUT_sel
Out[7:0]
8
3
7
4
LATCH/DFF_sel
nSET/nRST_sel
To Connection
Matrix Input [12]
ShRg_length [2:0]
1-bit NVM
7-bit NVM
LUT IN1
DFF data in
ShRg data in
LUT IN0
DFF CLK
ShRg CLK
From Connectinon
Matrix Output [29]
From Connectinon
Matrix Output [31]
LUT IN2
DFF nSet/nRST
ShRg nSet/nRST
LUT config
nQ/Q_sel
SET/RST_act_level
3
8 memory cells
D_in
Clk
nSET/nRST
SET/RST
S1
S0
000
111
.
.
.
[7]
3-bit LUT
S0
S1
S1
S0
S0
S1
S0
S1
From Connectinon
Matrix Output [33]
3
ShRg/LUT_sel
Out[7:0]
8
3
7
4
LATCH/DFF_sel
nSET/nRST_sel
To Connection
Matrix Input [13]
ShRg_length [2:0]
1-bit NVM
7-bit NVM
LUT IN1
DFF data in
ShRg data in
LUT IN0
DFF CLK
ShRg CLK
From Connectinon
Matrix Output [32]
From Connectinon
Matrix Output [34]
LUT IN2
DFF nSet/nRST
ShRg nSet/nRST
LUT config
nQ/Q_sel
SET/RST_act_level



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