ICSSSTUAF32865A

2

8-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

2

8-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

10

ICSSSTUAF32865A

7097/1

1

Timing Requirements Over Recommended Operating Free-Air Temperature

Range

Switching Characteristics Over Recommended Free Air Operating Range

(unless otherwise noted)

Symbol

Parameter

VDD = 1.8V ± 0.1V

Units

Min.

Max.

fCLOCK

Clock Frequency

410

MHz

tW

Pulse Duration; CLK, CLK HIGH or LOW

1

ns

tACT

Differential Inputs Active Time1

1

VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a

minimum time of tACT(max) after RESET is taken HIGH.

10

ns

tINACT

Differential Inputs Inactive Time2

2

VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum

time of tINACT(max) after RESET is taken LOW.

15

ns

tSU

Setup

Time

DCS0 before CLK

↑ , CLK↓, DCS and CSGateEN

HIGH; DCS1 before CLK

↑ , CLK↓, DCS0 and

CSGateEN HIGH

0.7

ns

DCSn, DODT, DCKE, and Dn after CLK

↑ , CLK↓

0.5

PARIN after CLK

↑ , CLK↓

0.5

tH

Hold

Time

DCSn, DODT, DCKE, and Dn after CLK

↑ , CLK↓

0.5

ns

PARIN after CLK

↑ , CLK↓

0.5

Symbol

Parameter

VDD = 1.8V ± 0.1V

Units

Min.

Max.

fMAX

Max Input Clock Frequency

410

MHz

tPDM

Propagation Delay, single bit switching, CLK

↑ to CLK↓to Qn

1.3

1.9

ns

tPDMSS

Propagation Delay, simultaneous switching, CLK

↑ to CLK↓to

Qn

2ns

tLH

LOW to HIGH Propagation Delay, CLK

↑ to CLK↓to PTYERR

1.2

3

ns

tHL

HIGH to LOW Propagation Delay, CLK

↑ to CLK↓to PTYERR

13

ns

tPHL

HIGH to LOW Propagation Delay, RESET

↓to Qn↓

3ns

tPLH

LOW to HIGH Propagation Delay, RESET

↓to PTYERR↑

3ns