HT6256

2

SIGNAL DEFINITIONS

A: 0-14

Address input pins which select a particular eight-bit word within the memory array.

DQ: 0-7

Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write

operation.

NCS

Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS

forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and

disables all input buffers. If this signal is not used it must be connected to VSS.

NWE

Negative write enable, when at a low level activates a write operation and holds the data output drivers in

a high impedance state. When at a high level NWE allows normal read operation.

NOE

Negative output enable, when at a high level holds the data output drivers in a high impedance state. When

at a low level, the data output driver state is defined by NCS and NWE. If this signal is not used it must be

connected to VSS.

CE*

External control of Chip Enable is an extra feature available only in other package options. Chip enable, when

at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition,

holds the data output drivers in a high impedance state and disables all the input buffers except the NCS input

buffer. If this signal is not used it must be connected to VDD.

TRUTH TABLE

Notes:

X: VI=VIH or VIL

XX: VSS

≤VI≤VDD

NOE=H: High Z output state maintained for

NCS=X, CE=X, NWE=X

FUNCTIONAL DIAGRAM

NCS

CE*

NWE

NOE

MODE

DQ

L

H

H

L

Read

Data Out

L

H

L

X

Write

Data In

H

X

XX

XX

Deselected

High Z

X

L

XX

XX

Disabled

High Z

NCS

A:0-8,12-13

CE*

NWE

NOE

WE • CS • CE

NWE • CS • CE • OE

Column Decoder

Data Input/Output

Row

Decoder

32,768 x 8

Memory

Array

A:9-11, 14

#

Signal

All controls must be

enabled for a signal to

pass. (#: number of

buffers, default = 1)

1 = enabled

Signal

4

DQ:0-7

(0 = high Z)

•

•

•

•

•

•

8

8

11