ICS950818

Power Down De-Assertion Mode

The power-up latency needs to be less than 1.BmS. this is the time from the de-asseration of the powerdown of the

ramping of the power supply until the time that stable clocks are output from the clock chip. If the SMBus Bit 6 of Byte

0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.

+- < 1.8mS ---+

PCIF

PCI

PD#

CPU@133MHz

________l.f"UUUU

CPU# @133MHz

3V66

USB48MHz

REF 14.318

Test Configuration Diagram

CLK408

Rs=33Ohms

5%

Rs=33Ohms

5%

Rp=49.9Ohms

1%

Rset=475 Ohms

1%

MULTSEL Pin must be High

Rp=49.9Ohms

1%

CPU 0.7V Configuration test load board termination

0825F-11/19/03

18

CPUCLKT test

point

CPUCLKC test

point