ICS91730

LOW EMI, SPREAD MODULATING, CLOCK GENERATOR

IDT®

LOW EMI, SPREAD MODULATING, CLOCK GENERATOR

3

ICS91730

REV F 061611

Table 1: Frequency Configuration (see I2C Byte0)

Above is the hard coded 5 bit (32 entry) ROM table.

FS3:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS4 can also be decoded from FS_IN1

latched input hardware pins.

FS_IN1

→ FS4. Upon power-up the default is to use hardware selection of FS_IN1 latched value.

FS3 = 0, FS2 = 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1).

To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power up

default of FS_IN1 = 1 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software selection by

switching this bit to a ‘1’ and then program the desired percentage by changing byte0 bits 7:3.

FS4

FS3

FS2

FS1

FS0

Sprd Type Sprd %

000

00

0.60

000

01

0.80

000

10

1.00

000

11

1.25

001

00

1.50

001

01

2.00

001

10

0.50

001

11

1.00

010

00

0.60

010

01

1.00

010

10

-0.80

010

11

CTR SPD

+/-0.3

011

00

1.50

011

01

1.75

011

10

2.00

011

11

2.50

100

00

3.00

100

01

1.25

100

10

0.40

100

11

0.50

101

00

0.70

101

01

1.00

101

10

1.20

101

11

1.50

110

00

0.60

110

01

0.80

110

10

1.00

110

11

1.25

111

00

1.50

111

01

2.00

111

10

0.50

111

11

1.00

DOWN

SPREAD

(-)

DOWN

SPREAD

(-)

48in/48out

66in/66out

DOWN

SPREAD

(-)

CENTER

SPD (+/-)

14in/27out

DOWN

SPREAD

(-)

CENTER

SPD (+/-)

14in/14out

27in/27out

CENTER

SPD (+/-)