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MPC850 Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc |
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MPC850 Datasheet(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 42 Freescale Semiconductor CPM Electrical Characteristics Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram 8.2 IDMA Controller AC Electrical Specifications Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42. Figure 39. IDMA External Requests Timing Diagram Table 14. IDMA Controller Timing Num Characteristic All Frequencies Unit Min Max 40 DREQ setup time to clock high 7.00 — ns 41 DREQ hold time from clock high 3.00 — ns 42 SDACK assertion delay from clock high — 12.00 ns 43 SDACK negation delay from clock low — 12.00 ns 44 SDACK negation delay from TA low — 20.00 ns 45 SDACK negation delay from clock high — 15.00 ns 46 TA assertion to falling edge of the clock setup time (applies to external TA)7.00 — ns CLKOUT DATA-IN 29 31 30 DATA-OUT 41 40 DREQ (Input) CLKOUT (Output) |
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