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PSD4235G2V-10UI Datasheet(PDF) 94 Page - STMicroelectronics |
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PSD4235G2V-10UI Datasheet(HTML) 94 Page - STMicroelectronics |
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94 / 100 page ![]() PSD4256G6V 94/100 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 49. ISC Timing Diagram Table 73. ISC Timing Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. Symbol Parameter Conditions -10 Unit Min Max tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 15 MHz tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 30 ns tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 30 ns tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 2 MHz tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 240 ns tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 240 ns tISCPSU ISC Port Set Up Time 11 ns tISCPH ISC Port Hold Up Time 5 ns tISCPCO ISC Port Clock to Output 26 ns tISCPZV ISC Port High-Impedance to Valid Output 26 ns tISCPVZ ISC Port Valid Output to High-Impedance 26 ns ISCCH TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO t ISCCL t ISCPH t ISCPSU t ISCPVZ t ISCPZV t ISCPCO t AI02865 |
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