ICS672-01/02

QUADRACLOCK QUADRATURE DELAY BUFFER

ZERO DELAY BUFFER

IDT™ / ICS™ QUADRACLOCK QUADRATURE DELAY BUFFER

3

ICS672-01/02

REV L 051310

External Components

The ICS672-01/02 requires a minimum number of external components for proper operation. Decoupling capacitors

of 0.01µF should be connected between VDD and GND on pins 11 and 12, and VDD and GND on pins 13 and 12,

and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series termination resistor of 33

Ω may

be used close to each clock output pin to reduce reflections.

Operation and Applications

The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input clock

(ICLK). Phase shifts of 0° (CLK0), 90° (CLK90), 180° (CLK180), and 270° (CLK270) are provided, plus one

feedback clock (FBCLK). All output clocks will be a multiple of the input clock, as determined by the table on page

2. Refer to the illustrations in Figure 1 and Figure 2.

FBCLK is connected to the feedback input (FBIN) to provide a zero delay through the ICS672-01/02. FBCLK has a

0° phase shift from ICLK.

ICLK

CLK0,

FBCLK

CLK90

CLK180

CLK270

Figure 1. Phase alignment of input and output clocks (x1 multiplier)

ICLK

CLK0,

FBCLK

CLK90

CLK180

CLK270

Figure 2. Phase alignment of input and output clocks (x2 multiplier)