841S012DI Datasheet

©2016 Integrated Device Technology, Inc

January 4, 2016

3

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1V

DD_REFOUT

Power

Output supply pin for REF_OUT.

7, 14, 28, 29

V

DD

Power

Core supply pins.

2,

3

REF_OUT0,

REF_OUT1

Output

Single-ended LVCMOS/LVTTL reference clock outputs.

23

Ω typical output impedance.

4, 5, 15, 27, 35,

36, 40, 46, 50,

54

GND

Power

Power supply ground.

6

REF_IN

Input

Pulldown Single-ended LVCMOS/LVTTL reference clock input.

8

REF_SEL

Input

Pulldown

Reference select pin. When HIGH selects REF_IN. When LOW,

selects crystal. LVCMOS/LVTTL interface levels. See Table 3E.

9,

10

XTAL_IN, XTAL_

OUT

Input

Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.

External tuning capacitor must be used for proper operation.

11

BYPASS

Input

Pulldown

When HIGH bypasses PLL. When LOW, selects PLL.

LVCMOS/LVTTL interface levels. See Table 3J.

12

REF_OE

Input

Pulldown

Active HIGH REF_OUT enables/disables pin.

LVCMOS/LVTTL interface levels. See Table 3H.

13

nMR

Input

Pullup

Active LOW Master Reset. When logic LOW, the internal dividers are reset

and the outputs are in high impedance (HI-Z). When logic HIGH, the internal

dividers and the outputs are enabled.

LVCMOS/LVTTL interface levels. See Table 3I.

16,

17

SSC1,

SSC0

Input

Pullup

SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D.

18,

19,

20

F_SELB2, F_

SELB1,

F_SELB0

Input

Pulldown

Frequency select pins for QBx outputs. See Table 3B.

LVCMOS/LVTTL interface levels.

21,

22,

23

F_SELC2, F_

SELC1,

F_SELC0

Input

Pulldown

Frequency select pins for QC output. See Table 3C.

LVCMOS/LVTTL interface levels.

24,

25

F_SELA1, F_

SELA0

Input

Pulldown

Frequency select pins for QAx/nQAx outputs. See Table 3A.

LVCMOS/LVTTL interface levels.

26

QA_OE

Input

Pullup

Output enable pin for Bank A outputs. See Table 3F. LVCMOS/LVTTL inter-

face levels.

30, 31

32, 33

nQA1, QA1

nQA0, QA0

Output

Differential Bank A clock outputs. HCSL interface levels.

34

IREF

Output

External fixed precision resistor (475

Ω) from this pin to ground provides a

reference current used for differential current-mode QAx/nQAx clock outputs.

37, 38

V

DDA

Power

Analog supply pin.

39

QBC_OE

Input

Pullup

Output enable pin for Bank B and Bank C outputs.

LVCMOS/LVTTL Interface levels. See Table 3G.

41

QC

Output

Single-ended Bank C clock output. LVCMOS/LVTTL interface levels.

18

Ω typical output impedance.

42

V

DDOC

Power

Output supply pin for QC LVCMOS output.

43, 48, 52, 56

V

DDOB

Power

Output supply pins for QBx LVCMOS outputs.

44, 45,

47, 49,

51, 53, 55

QB0, QB1, QB2,

QB3, QB4, QB5,

QB6

Output

Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.

18

Ω typical output impedance.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.