SN250 datasheet(56/130 Pages) STMICROELECTRONICS

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Functional description—application modules

SN250

56/130

SC1_UARTSTAT [0x44A4]

SC1_RATELIN [0x44B0]

0-R

SC1_

UARTTXIDLE

SC1_

UARTPARERR

SC1_

UARTFRMERR

SC1_

UARTRXOVF

SC1_

UARTTXFREE

SC1_

UARTRXVAL

SC1_

UARTCTS

0-R

1-R

0-R

SC1_UARTTXIDLE

[6]

This bit is set when the transmit FIFO is empty and the transmitter is idle.

SC1_UARTPARERR

[5]

This bit is set when the receive FIFO has seen a parity error. This bit clears when the

data register (SC1_DATA) is read.

SC1_UARTFRMERR

[4]

This bit is set when the receive FIFO has seen a frame error. This bit clears when

the data register (SC1_DATA) is read.

SC1_UARTRXOVF

[3]

This bit is set when the receive FIFO has been overrun. This bit clears when the data

SC1_UARTTXFREE

[2]

This bit is set when the transmit FIFO is ready to accept at least one byte.

SC1_UARTRXVAL

[1]

This bit is set when the receive FIFO contains at least one byte.

SC1_UARTCTS

[0]

This bit shows the current state of the nCTS input signal at the nCTS pin (pin 19,

GPIO11). When CTS = 1, the signal is asserted (== TTL logic 0, GPIO is low, ’XON’,

RS232 positive voltage), the transmission will proceed. When CTS = 0, the signal is

deasserted (== TTL logic 1, GPIO is high, ’XOFF’, RS232 negative voltage),

transmission is inhibited at the end of the current character. Any characters in the

transmit buffer will remain there.

0-R

SC1_RATELIN

0-R

0-RW

SC1_RATELIN

[3:0]

The linear component (LIN) of the clock rate as seen in the equation:

Rate

24 MHz

2LIN

() 2

EXP

⋅⋅

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