DSP56321RMSLASHD datasheet(39/88 Pages) NXP

No. de pieza	DSP56321RM/D

Descripción Electrónicos	24-Bit Digital Signal Processor

PDF	88 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NXP [NXP Semiconductors]

Página de inicio	http://www.nxp.com

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39 / 88 page

2-15

AC Electrical Characteristics

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs.

These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a

result of this delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is

deasserted. This is the reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is

exposed to other DSP56300 components that are potential masters on the same bus. If BG input is

asserted before that time, and BG is asserted and BB is deasserted, another DSP56300 component may

assume mastership at the same time. Therefore, some non-overlap period between one BG input active to

another BG input active is required. Timing 251 ensures that overlaps are avoided.

Figure 2-12. Asynchronous Bus Arbitration Timing

BG1

251

BG2

250

250+251

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321RM/D Datasheet(PDF) 39 Page - NXP Semiconductors