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June 17, 2005

IDT 89TSF552

*Notice: The information in this document is subject to change without notice

89TSF552 Functional Block Diagram

89TSF552 Pin Description

Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions.

In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bidirectional, and P for power.

Signal Name

I/O Type

Dir.

Freq.

Remarks

SYS_CLK (pin A21)

3.3V LVTTL

I

125 MHz

N/A

PLL_SYS_LCK (pin B19)

3.3V LVTTL

O

—

N/A

PLL_RST (pin C22)

3.3V LVTTL

I

—

N/A

PLL_DIV_RST_N (pin D22)

3.3V LVTTL

I

—

33K

Ω internal pullup

PLL_SYS_VSSA (pin J20)

AVSS

P

—

33K

Ω internal pullup

PLL_SYS_VDDA (pin K20)

3.3V AVDD

P

—

Supply

PLL_SYS_VDD (pin H21)

1.8V VDD

P

—

Supply

PLL_SYS_VSS (pin J21)

VSS

P

—

Supply

Table 1 89TSF552 PLL Control and Power Pins

data

2.5 Gbps

SerDes

Ingress

CSIX

Receiver

(ICRX)

Egress

CSIX

Transmitter

(ECTX)

Ingress

VOQs

(IVOQ)

request

Request

Processor

(RP)

C2C

Diagnostic

Loopback

2.5 Gbps

SerDes

Egress Buffer

(EBUFF)

Processor

Interface

Processor

up to

33 MHz

125

MHz

CSIX

domain

(24)

(24)

(256 + 2)

To

89TSF500

CSIX

Loopback

CSIX domain: 500 MHz to 1.0 GHZ, 16 bits.

16 or 32 bits

16 or 32 bits

Egress to

IVOQ

Loopback

SerDes

line-side

loopback

SerDes

loopback