PAC1941T-1ESLASH4MX. datasheet(35/96 Pages) MICROCHIP

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 2021 Microchip Technology Inc.

DS20006543A-page 35

PAC194X

6.4

I2C/SMBus Protocols

The PAC194X supports Write Byte, Block Write, Read

Byte, Block Read, Send Byte and Receive Byte as

valid protocols.

It does not respond to the Alert Response Address

protocol. It responds to the I2C General Call Address.

All the protocol charts listed below use the convention

in Table 6-2.

6.5

Auto-Incrementing Pointer

The PAC194X has an auto-incrementing address

pointer. The pointer has two loops for auto-increment-

ing, a read loop and a write loop.

The read loop includes all the readable registers, all

the configuration and control registers, the results reg-

isters, Product ID, Manufacturer ID and Revision ID

registers.

The write loop includes only the writable control and

configuration registers.

Neither loop includes the REFRESH commands.

The read loop skips the inactive channels, if some

channels are disabled. This automatic channel skip-

ping feature can be disabled by setting the NO SKIP

bit in Register 7-10.

There are two cases to consider when a channel is

disabled and a read is performed on it:

• the SKIP function is OFF, the register address will

be ACKed and the data returned are FFh,

followed by a NACK.

• the SKIP function is ON, the register address will

be NACKed and the data returned are FFh,

followed by a NACK.

In the first case, the channel address is still part of the

I2C/SMBus ACK the address. In the second case, the

channel address is removed from the register map and

becomes an invalid address, thus the I2C/SMBus

NACK the address. In both cases, the value returned

is FFh, because the channel is disabled (invalid) and

the I2C/SMBus NACK the data. See Figure 6-2 for a

graphic representation.

TABLE 6-2:

PROTOCOL FORMAT

Data Sent to Device

Data Sent to the Host

# of bits sent

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